SR Latch using NAND gates

SR Latch using NAND Gates – Interactive

Toggle S' and R' inputs and observe the latch state. Inputs are **active-LOW**.

S':

R':

Outputs: Q0 Q̅1

Circuit Diagram

Timing Diagram (Input Combinations)

Current: S'=1, R'=1 → Hold State (Q=0, Q̅=1)