D Latch

D Latch using SR-based NAND Latch

Toggle D and Enable (E). When E = 1, Q follows D; when E = 0, Q holds.

D: 0

E: 0

Outputs: Q0 Q̅1

Circuit Diagram

D latch built from SR NAND latch with input gating.

Timing Diagram

Example behavior over t₀–t₃ for different D and E combinations.

Current: D=0, E=0 → Q holds (Q=0, Q̅=1)