JK Flip Flop

JK Flip-Flop (NAND) – Interactive

Toggle J, K, and CLK inputs and observe the flip-flop state. **CLK=1** enables operation.

J:

K:

CLK:

Outputs: Q0 Q̅1

Circuit Diagram [Image of SR Latch using NAND gates circuit diagram]

Timing Diagram (J-K Combinations at CLK=1)

Current: J=0, K=0, CLK=0 → Hold State (CLK Disabled) (Q=0, Q̅=1)