T Flip-Flop (NAND) – Interactive
Toggle T and CLK inputs and observe the flip-flop state. **CLK=1** enables operation.
T:
CLK:
Outputs:
Q0
Q̅1
Circuit Diagram
[Image of T Flip-Flop using NAND gates]
Timing Diagram (T Input Combinations)
Current: T=0, CLK=0 → Hold State (CLK Disabled) (Q=0, Q̅=1)
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